The present invention relates to a clock synchronization delay control circuit for generating a clock signal (hereinafter called an internal clock signal) that is to be used in a semiconductor integrated circuit and is synchronized with, for example, a clock signal (hereinafter called an external clock signal) supplied from outside into the semiconductor integrated circuit.
Recently, acceleration of the processing in a computer system has been required, and therefore, a clock synchronization memory operated in synchronization of a clock signal of a synchronous DRAM and the like is employed. Such a clock synchronization memory uses the internal clock signal synchronous with the external clock signal that is supplied from the outside to control the memory. When a delay is generated between the internal clock signal and the external clock signal, a malfunction of the circuit occurs. Particularly, in a case where the operating rate is high, the malfunction easily occurs even if a slight delay is generated. For this reason, a clock synchronization delay control circuit is integrated to VLSI to synchronize the internal clock with the external clock.
First, the principle in the operations of the clock synchronization delay control circuit will be briefly explained. FIG. 27 is a block diagram showing a conventional clock synchronization delay control circuit. This circuit is an STBD (Synchronous Traced Backward Delay) disclosed in Jpn. Pat. Appln. KOKAI Publication No. 10-69326. FIG. 28 is a waveform chart explaining the principle in the operations of the clock synchronization delay control circuit. In the following explanations, a case where the output of a delay unit for forward pulse at the N-th stage is connected to the input of a status holding circuit at the N-th stage and the output of the status holding circuit at the N-th stage is connected to the input of a delay unit for backward pulse at the N-1-th stage, will be exemplified so that the operations of the STBD can easily be understood.
It is assumed that an external clock ExtCLK of a cycle .tau. shown in FIG. 28 is supplied to a receiver 11 of FIG. 27. The external clock ExtCLK is waveform-shaped by the receiver 11 and then amplified. A signal CLK outputted from the receiver 11 is delayed Trc from the external clock ExtCLK (by the receiver 11). The signal CLK is supplied to a control pulse generation circuit 13, a delay monitor (DM) 12 and a delay line 18 for backward pulse. The control pulse generation circuit 13 converts the signal CLK into a pulse and generates a control pulse signal P. The delay monitor 12 has a delay time Trc+Tdr that is equal to the sum of the delay time Trc of the receiver 11 and the delay time Tdr of a driver 19. Output signal FCL of the delay monitor 12 is supplied to the delay line 15 for forward pulse after a delay of Trc+ Tdr from the output signal CLK of the receiver 11.
The delay line 15 for forward pulse is constituted by cascade connection to a delay unit (DU) 14 for forward pulse. When the control pulse signal P is at a low level, each delay unit 14 propagates a forward pulse from the delay unit of the front stage, to the delay unit of the back stage. Further, when the control pulse signal P is at a high level, the each delay unit 14 outputs the low-level signal to stop the propagation of the forward pulse signal and initialize the delay line. The signal FCL is propagated in the delay line 15 for forward pulse during a period .tau.-(Trc+Tdr) from the start of the propagation to a time when the control pulse signal P becomes at a high level.
A status holding circuit 16 stores the propagated state of the forward pulse signal. In accordance with the stored information, the status holding circuit 16 controls the delay line 18 for backward pulse so that the propagation time of the backward pulse signal propagated in the delay line 18 for backward pulse is equal to the propagation time of the forward pulse signal. The status holding circuit 16 has two kinds of the states, i.e. a set state and a reset state, and outputs the control signal responding to the state to a delay unit (DU) 17 for backward pulse. In FIG. 27, "S" represents the set state and "R" represents the reset state. The delay unit 17 controlled by the status holding circuit 16 in the set state "S" outputs a logic value equal to the output of the delay unit 17 of the back stage to the delay unit of the front stage. The delay unit 17 controlled by the status holding circuit 16 in the reset state "R" outputs the output signal of the receiver 11 to the delay unit of the front stage. All the status holding section 16 are initially in the reset state. The status holding circuit 16 remains in the reset state "R" if the forward pulse signal is not propagated to the connected delay unit 14 when the control pulse signal P is at a low level. On the other hand, the status holding section 16 becomes in the set state "S" if the forward pulse signal is propagated thereto when the control pulse signal P is at a low level. Further, the status holding section 16 becomes in the reset state "R" if the backward pulse signal is propagated to the delay unit 17 when the control pulse signal P is at a high level.
When the control pulse signal P becomes at a high level, the signal CLX is at a high level. Therefore, the high-level signal is supplied to the delay unit 17 controlled by the status holding section 16 of the N+1-th and the following stages in the reset state "R". If the number of stages at which the forward pulse signal is propagated is N, the status holding sections 16 at the first to N-th stages are in the set state "S". Therefore, the signal which is output from the delay unit 17 of the N-th stage controlled by the status holding section of the N+1-th stage in the reset state "R", is propagated as the backward pulse signal by the delay unit 17 at N-1th stage to first stage. Therefore, the number of stages of the delay units to which the backward pulse signal is propagated becomes equal to the number of stages of the delay units to which the forward pulse signal is propagated. When the delay units are designed so that the delay time thereof is equally .DELTA.du, the signal CLX which is input to the delay line 18 for backward pulse is propagated in the delay line and then output, during the same period .tau.-(Trc+Tdr) as the period in which the forward pulse signal is propagated. The output signal RCL of the delay line 18 for backward pulse is supplied to the driver 19. Output signal IntCLK of the driver 19 is delayed by the delay time Tdr thereof. If the delay time from the supply of the external clock signal ExtCLK to the generation of the internal clock signal IntCLK is .DELTA.total, .DELTA.total can be obtained in Equation (1). EQU .DELTA.total=Trc+(Trc+Tdr)+2{.tau.-(Trc+Tdr)}+Tdr=2.tau. (1)
As evident from Equation (1), the delay time of the internal clock signal to the external clock signal is 2 .tau., and consequently, the external clock signal and the internal clock signal are synthesized with one another.
In the delay line constituting the clock synchronization delay control circuit such as the above-described STBD, the direction of the pulse signal propagated to the delay line 15 for forward pulse is opposite to that of the pulse signal propagated in the delay line 18 for backward pulse.
FIG. 29 schematically shows the structure of the delay units constituting the delay line 15 for forward pulse and the delay line 18 for backward pulse. As shown in the figure, a position of an input terminal IN is designed to be opposite to the position of an output terminal OUT in each of the delay units 14 and delay unit 17.
Direction from IN to OUT of each delay units 14 constituting delay line 15 is same to direction of forward pulse propagating the delay line 15. Similarly, direction from IN to OUT of each delay units 14 constituting delay line 18 is same to direction of backward pulse propagating the delay line 18. Direction of each delay unit is opposite to that of delay unit 17.
FIG. 30 specifically shows the delay units 14 and 17 shown in FIG. 29, illustrating a layout of constituting each of the delay units 14 and 17 with two inverter circuits. FIG. 31 shows a case where a mask is displaced in a direction of an arrow (a direction of a channel length of a MOS transistor (i.e. a direction from a source area to a drain area)) at the time of producing the delay units 14 and 17 shown in FIG. 29. The mask displacement means that an exposure pattern shifts. Thus, when the mask is displaced, the characteristics of the delay units 14 for forward pulse and the delay units 17 for backward pulse will become different. For this reason, the delay time of the delay unit 14 for forward pulse is not equal to that of the delay unit 17 for backward pulse.
When the delay time of the delay unit 14 for forward pulse is represented by tdu-1 and the delay time of the delay unit 17 for backward pulse is represented by tdu-s, the relationship of the delay time in the circuit shown in FIG. 29 can be represented as shown in FIG. 32. For this reason, the forward pulse is propagated to the N-th stage of the delay unit for forward pulse during .tau.-(Trc+Tdr), and when the backward pulse is propagated from the N-th stage of the delay unit for backward pulse an error as represented by the following equation is generated. EQU .vertline.tdu-1-tdu-s.vertline..times.N
This error causes an error to be generated between the external clock signal and the internal clock signal. This problem is applied to a clock synchronization delay control circuit using two delay lines whose directions are opposite similarly to the STBD.
FIGS. 33 to 35A and 35B show another example of the conventional clock synchronization delay control circuit using two or more delay lines that have opposite directions for propagation of a pulse.
In FIG. 33, a delay line for forward pulse 27 and a delay line for backward pulse 28 constitute unit delay units 31 and 32 with NAND circuits and NOR circuits. FIGS. 33 and 34 show a circuit disclosed in Jpn. Pat. Appln. KOKAI Publication No. 11-272356. In this circuit, a NAND circuit and an inverter circuit are used for delay units 4-2 and 5-2 constituting a delay line 4 for forward pulse and a delay line 5 for backward pulse. FIG. 35A shows a circuit disclosed in Jpn. Pat. Appln. KOKAI Publication No. 11-31952. In this circuit, a delay line for forward pulse 6 and a delay line 7 for backward pulse are constituted by delay units 11 and 12. For example the delay line 6 for forward pulse and the delay line 7 for backward pulse are constituted by using a plurality of clocked inverter circuits 31 as shown in FIG. 35B.
FIG. 36A shows a system different from that of the clock synchronization delay control circuit allowing the internal clock signal to be synchronized with the external clock signal in two cycles as shown in FIG. 27. The clock synchronization delay control circuit of this system is constituted by a receiver, a delay monitor, a control circuit, input control circuits, delay units and an output control circuit (serving also as a driver). A delay line 1 and a delay line 2 are constituted by a plurality of delay units provided in a cascade connection. The delay unit for forward pulse and the delay unit for backward pulse shown in FIG. 27 transmit the pulses in only one direction. On the other hand, the delay units constituting the delay lines 1 and 2 shown in FIG. 36A transmit the pulses in both the forward and backward directions. FIG. 36B shows an example of the delay unit shown in FIG. 36A. In the structures shown in FIGS. 36A and 36B, too, an error occurs in the delay time of the delay line due to the displacement of the mask and the irregularity of the process, and thereby the performance is deteriorated.